[PATCH v2 07/16] RISC-V: drop FCVT.Q.L{,U} forms with rounding mode operand
Project / Subsystem
binutils / risc-v
Date
2026-05-15
Proposer
Jan Beulich <jbeulich@suse.com>
Source type
public_inbox
Consensus
Proposed
Sentiment
—/10
Technical tradeoffs
- • Simplified instruction definitions.
- • Removed a potentially confusing operand from the assembler syntax.
All attributes
- project
- binutils
- subsystem
- risc-v
- patch_id
- —
- discussion_id
- 22f4c3a6-01a8-4ae4-8359-5d5ad3470b8b@suse.com
- source_type
- public_inbox
- title
- [PATCH v2 07/16] RISC-V: drop FCVT.Q.L{,U} forms with rounding mode operand
- headline
- RISC-V: drop FCVT.Q.L{,U} forms with rounding mode operand
- tldr
- Removes the rounding mode operand from the `FCVT.Q.L` and `FCVT.Q.LU` RISC-V instructions as it has no effect.
- proposer
- Jan Beulich <jbeulich@suse.com>
- consensus
- Proposed
- outcome
- proposed
- sentiment_score
- —
- technical_tradeoffs
-
- • Simplified instruction definitions.
- • Removed a potentially confusing operand from the assembler syntax.
- series_id
- binutils:risc-v: drop fcvt.q.l{,u} forms with rounding mode operand
- series_role
- reply
- series_parts
- []
- tags
-
- • risc-v
- • instruction set
- • opcode
- • rounding mode
- • assembler
- bugzilla_url
- —
- date
- 2026-05-15T00:00:00.000Z
[PATCH v2 07/16] RISC-V: drop FCVT.Q.L{,U} forms with rounding mode operand
This patch removes the rounding mode operand from the FCVT.Q.L and FCVT.Q.LU RISC-V instructions in the opcode table. The rounding mode has no effect on these instructions, so allowing the operand is misleading. This change aligns these instructions with similar ones (FCVT.D.W, FCVT.Q.W) and simplifies the opcode definitions.