[PATCH 1/2] RISC-V: Add ARC-V APEX assembler support
Project / Subsystem
binutils / risc-v
Date
2026-05-25
Proposer
Luis Silva <Luis.Silva1@synopsys.com>
Source type
public_inbox
Consensus
Proposed
Sentiment
—/10
Technical tradeoffs
- • The implementation requires adding a new directive, `.extInstruction`, which may introduce compatibility issues with existing assembly code.
- • Emitting metadata into a COMDAT ELF section increases the size of the object file.
All attributes
- project
- binutils
- subsystem
- risc-v
- patch_id
- —
- discussion_id
- 20260525133052.1885254-2-luiss@synopsys.com
- source_type
- public_inbox
- title
- [PATCH 1/2] RISC-V: Add ARC-V APEX assembler support
- headline
- RISC-V: Add support for ARC-V APEX assembler
- tldr
- This patch adds support for the ARC-V APEX extension, allowing dynamic custom instruction definition in the RISC-V assembler.
- proposer
- Luis Silva <Luis.Silva1@synopsys.com>
- consensus
- Proposed
- outcome
- proposed
- sentiment_score
- —
- technical_tradeoffs
-
- • The implementation requires adding a new directive, `.extInstruction`, which may introduce compatibility issues with existing assembly code.
- • Emitting metadata into a COMDAT ELF section increases the size of the object file.
- series_id
- binutils:risc-v: add arc-v apex assembler support
- series_role
- reply
- series_parts
- []
- tags
-
- • binutils
- • risc-v
- • assembler
- • ARC-V APEX
- • custom instructions
- bugzilla_url
- —
- date
- 2026-05-25T00:00:00.000Z
[PATCH 1/2] RISC-V: Add ARC-V APEX assembler support
This patch introduces support for ARC-V APEX (ARC Processor EXtension) to the RISC-V assembler. APEX enables users to dynamically define custom instructions using the Custom-0 encoding space. The patch implements the .extInstruction directive for registering new instructions, which emit metadata into a COMDAT ELF section. This allows instruction definitions to be preserved in the linked object.