[PATCH 2/2] RISC-V: Add ARC-V APEX disassembler support
Project / Subsystem
binutils / risc-v
Date
2026-05-25
Proposer
Luis Silva <Luis.Silva1@synopsys.com>
Source type
public_inbox
Consensus
Proposed
Sentiment
—/10
Technical tradeoffs
- • Dynamically allocating memory for `riscv_opcode` entries adds complexity and potential memory management issues.
- • Reading and processing metadata at startup may increase startup time.
All attributes
- project
- binutils
- subsystem
- risc-v
- patch_id
- —
- discussion_id
- 20260525133052.1885254-3-luiss@synopsys.com
- source_type
- public_inbox
- title
- [PATCH 2/2] RISC-V: Add ARC-V APEX disassembler support
- headline
- RISC-V: Add support for ARC-V APEX disassembler
- tldr
- This patch adds disassembler support for ARC-V APEX instructions by reading metadata from ELF sections.
- proposer
- Luis Silva <Luis.Silva1@synopsys.com>
- consensus
- Proposed
- outcome
- proposed
- sentiment_score
- —
- technical_tradeoffs
-
- • Dynamically allocating memory for `riscv_opcode` entries adds complexity and potential memory management issues.
- • Reading and processing metadata at startup may increase startup time.
- series_id
- binutils:risc-v: add arc-v apex disassembler support
- series_role
- reply
- series_parts
- []
- tags
-
- • binutils
- • risc-v
- • disassembler
- • ARC-V APEX
- • custom instructions
- bugzilla_url
- —
- date
- 2026-05-25T00:00:00.000Z
[PATCH 2/2] RISC-V: Add ARC-V APEX disassembler support
This patch adds support to the RISC-V disassembler for ARC-V APEX instructions. The disassembler reads metadata from .riscvapex.* ELF sections (emitted by the assembler) to reconstruct instruction definitions at startup. The metadata is deserialized into a lookup table, and the disassembler attempts to decode instructions using this table when the standard opcode table produces no match.