Re: [PATCH v3 02/13] RISC-V: EEW64 checking
Project / Subsystem
binutils / risc-v
Date
2026-07-21
Proposer
Nelson Chu <nelson.chu1990@gmail.com>
Source type
public_inbox
Consensus
Proposed
Sentiment
—/10
Technical tradeoffs
- • Simplifies checks by introducing a new instruction class, potentially improving maintainability.
All attributes
- project
- binutils
- subsystem
- risc-v
- patch_id
- —
- discussion_id
- CAHT-pJywaC76VOWGdEFbKVDkTLxcij0fLmJyAN86V+4rPuay=A@mail.gmail.com
- source_type
- public_inbox
- title
- Re: [PATCH v3 02/13] RISC-V: EEW64 checking
- headline
- RISC-V: EEW64 checking
- tldr
- Discussion on correct handling of RISC-V Zve64x extension checks in assembler and disassembler.
- proposer
- Nelson Chu <nelson.chu1990@gmail.com>
- consensus
- Proposed
- outcome
- proposed
- sentiment_score
- —
- technical_tradeoffs
-
- • Simplifies checks by introducing a new instruction class, potentially improving maintainability.
- series_id
- binutils:risc-v: eew64 checking
- series_role
- reply
- series_parts
- []
- tags
-
- • risc-v
- • extensions
- • binutils
- • assembler
- • disassembler
- bugzilla_url
- —
- date
- 2026-07-21T00:00:00.000Z
Re: [PATCH v3 02/13] RISC-V: EEW64 checking
This discussion addresses the correct implementation of checks for the RISC-V Zve64x extension in binutils’ assembler and disassembler. Jan Beulich points out that the disassembler should also use the INSN_V_EEW64 flag and questions the redundancy of Zve32x checks. Nelson Chu agrees with this, suggesting that a new INSN_CLASS_ZVE64X would be a more appropriate way to handle these checks, aligning with the assembler’s logic and simplifying the code.