Re: [PATCH v3 04/13] bfd/RISC-V: Zv{b,k}* imply Zve32x

Project / Subsystem

binutils / bfd/risc-v

Date

2026-07-21

Proposer

Nelson Chu <nelson.chu1990@gmail.com>

Source type

public_inbox

Consensus

Proposed

Sentiment

/10

Technical tradeoffs

  • Ensuring correct adherence to the RISC-V specification versus maintaining compatibility with existing binutils handling.

All attributes

project
binutils
subsystem
bfd/risc-v
patch_id
discussion_id
CAHT-pJwkccCTquFHm-grzdWTLX1DAnpK6yprUFAztB0Px1qNOg@mail.gmail.com
source_type
public_inbox
title
Re: [PATCH v3 04/13] bfd/RISC-V: Zv{b,k}* imply Zve32x
headline
RISC-V: Zv{b,k}* imply Zve32x
tldr
Discussion on correct ordering of RISC-V extensions in binutils, specifically concerning 'zve32x' implication.
proposer
Nelson Chu <nelson.chu1990@gmail.com>
consensus
Proposed
outcome
proposed
sentiment_score
technical_tradeoffs
  • Ensuring correct adherence to the RISC-V specification versus maintaining compatibility with existing binutils handling.
series_id
binutils:bfd/risc-v: zv{b,k}* imply zve32x
series_role
reply
series_parts
[]
tags
  • risc-v
  • extensions
  • binutils
  • isa
  • specification
bugzilla_url
date
2026-07-21T00:00:00.000Z

Re: [PATCH v3 04/13] bfd/RISC-V: Zv{b,k}* imply Zve32x

This discussion centers on the correct placement and implication of RISC-V extensions in binutils, specifically addressing whether ‘zve32x’ should be implied by extensions like ‘zvbc’ and ‘zvkb’. Nelson Chu argues for the current alphabetical ordering within categories based on the ISA specification, while also noting potential deviations from naming rules in ratified extensions. Jan Beulich’s comments raise questions about the ordering within the riscv_supported_std_z_ext tables.