[PATCH v4 02/12] bfd/RISC-V: Zve{32,64}f don't need to explicitly imply Zvl{32,64}b
Project / Subsystem
binutils / bfd/risc-v
Date
2026-07-24
Proposer
Jan Beulich <jbeulich@suse.com>
Source type
public_inbox
Consensus
Proposed
Sentiment
—/10
Technical tradeoffs
- • Reduces complexity in the BFD RISC-V extension handling.
- • Leverages existing implications to avoid redundant definitions.
All attributes
- project
- binutils
- subsystem
- bfd/risc-v
- patch_id
- —
- discussion_id
- 93e2c76e-edd5-4293-9d99-04d6bf30b1f4@suse.com
- source_type
- public_inbox
- title
- [PATCH v4 02/12] bfd/RISC-V: Zve{32,64}f don't need to explicitly imply Zvl{32,64}b
- headline
- BFD/RISC-V: Zve{32,64}f do not need to explicitly imply Zvl{32,64}b
- tldr
- Removes redundant RISC-V CPU extension implications in BFD to avoid excess processing.
- proposer
- Jan Beulich <jbeulich@suse.com>
- consensus
- Proposed
- outcome
- proposed
- sentiment_score
- —
- technical_tradeoffs
-
- • Reduces complexity in the BFD RISC-V extension handling.
- • Leverages existing implications to avoid redundant definitions.
- series_id
- binutils:bfd/risc-v: zve{32,64}f don't need to explicitly imply zvl{32,64}b
- series_role
- reply
- series_parts
- []
- tags
-
- • binutils
- • bfd
- • risc-v
- • compiler
- • extensions
- bugzilla_url
- —
- date
- 2026-07-24T00:00:00.000Z
[PATCH v4 02/12] bfd/RISC-V: Zve{32,64}f don't need to explicitly imply Zvl{32,64}b
This patch simplifies RISC-V CPU extension handling in binutils’ BFD library. It removes explicit implications for Zvl{32,64}b when Zve{32,64}f extensions are present. The existing Zve{32,64}x implications already cover the necessary dependencies, making the explicit Zvl settings redundant and subject to excess processing.