[PATCH v4 06/12] RISC-V: check operands for Zdinx in RV32
Project / Subsystem
binutils / risc-v
Date
2026-07-24
Proposer
Jan Beulich <jbeulich@suse.com>
Source type
public_inbox
Consensus
Proposed
Sentiment
—/10
Technical tradeoffs
- • Ensures correct instruction encoding for Zdinx by validating register operands.
- • Introduces a new macro (`RV32_EVEN_CHECK`), potentially duplicated or refactored later based on reuse with Zilsd.
All attributes
- project
- binutils
- subsystem
- risc-v
- patch_id
- —
- discussion_id
- 8873df38-aa72-4643-91b3-4037643b2717@suse.com
- source_type
- public_inbox
- title
- [PATCH v4 06/12] RISC-V: check operands for Zdinx in RV32
- headline
- RISC-V: check operands for Zdinx in RV32
- tldr
- Add operand checks for the RISC-V Zdinx extension specifically for RV32.
- proposer
- Jan Beulich <jbeulich@suse.com>
- consensus
- Proposed
- outcome
- proposed
- sentiment_score
- —
- technical_tradeoffs
-
- • Ensures correct instruction encoding for Zdinx by validating register operands.
- • Introduces a new macro (`RV32_EVEN_CHECK`), potentially duplicated or refactored later based on reuse with Zilsd.
- series_id
- binutils:risc-v: check operands for zdinx in rv32
- series_role
- reply
- series_parts
- []
- tags
-
- • binutils
- • risc-v
- • assembler
- • extension
- • validation
- bugzilla_url
- —
- date
- 2026-07-24T00:00:00.000Z
[PATCH v4 06/12] RISC-V: check operands for Zdinx in RV32
This patch enhances the RISC-V assembler by adding operand checks for the Zdinx extension in RV32. Similar to the Zilsd extension, it enforces that register pair operands must have their least significant bit clear. This validation is implemented using a new RV32_EVEN_CHECK macro, ensuring correct instruction encoding for this extension.