[PATCH v4 07/12] RISC-V: check operands for Zqinx
Project / Subsystem
binutils / risc-v
Date
2026-07-24
Proposer
Jan Beulich <jbeulich@suse.com>
Source type
public_inbox
Consensus
Proposed
Sentiment
—/10
Technical tradeoffs
- • Improves correctness by enforcing operand constraints for the Zqinx extension.
- • Relies on inferred rules due to the lack of formal specification for Zqinx register pair encoding.
All attributes
- project
- binutils
- subsystem
- risc-v
- patch_id
- —
- discussion_id
- a51cf9e2-baf6-4fba-bcae-33fb33d22c7e@suse.com
- source_type
- public_inbox
- title
- [PATCH v4 07/12] RISC-V: check operands for Zqinx
- headline
- RISC-V: check operands for Zqinx
- tldr
- Add operand checks for the RISC-V Zqinx extension in RV32 and RV64.
- proposer
- Jan Beulich <jbeulich@suse.com>
- consensus
- Proposed
- outcome
- proposed
- sentiment_score
- —
- technical_tradeoffs
-
- • Improves correctness by enforcing operand constraints for the Zqinx extension.
- • Relies on inferred rules due to the lack of formal specification for Zqinx register pair encoding.
- series_id
- binutils:risc-v: check operands for zqinx
- series_role
- reply
- series_parts
- []
- tags
-
- • binutils
- • risc-v
- • assembler
- • extension
- • validation
- bugzilla_url
- —
- date
- 2026-07-24T00:00:00.000Z
[PATCH v4 07/12] RISC-V: check operands for Zqinx
This patch introduces operand checks for the RISC-V Zqinx extension in both RV32 and RV64. It enforces that register pair operands must have specific low bits clear: the least significant bit for RV64 and the two least significant bits for RV32. This validation is crucial for correct instruction encoding, especially since the Zqinx extension’s exact specifications for register pairs are not formally defined.