[PATCH v4 04/12] RISC-V: drop FCVT.Q.L{,U} forms with rounding mode operand
Project / Subsystem
binutils / risc-v
Date
2026-07-24
Proposer
Jan Beulich <jbeulich@suse.com>
Source type
public_inbox
Consensus
Proposed
Sentiment
—/10
Technical tradeoffs
- • Simplifies the opcode table by removing incorrect instruction forms.
- • Removes the possibility of users incorrectly specifying a rounding mode for these instructions.
All attributes
- project
- binutils
- subsystem
- risc-v
- patch_id
- —
- discussion_id
- e790534c-6de5-4595-bcd3-34ab3c243cab@suse.com
- source_type
- public_inbox
- title
- [PATCH v4 04/12] RISC-V: drop FCVT.Q.L{,U} forms with rounding mode operand
- headline
- RISC-V: drop FCVT.Q.L{,U} forms with rounding mode operand
- tldr
- Remove redundant floating-point conversion instructions from RISC-V assembler.
- proposer
- Jan Beulich <jbeulich@suse.com>
- consensus
- Proposed
- outcome
- proposed
- sentiment_score
- —
- technical_tradeoffs
-
- • Simplifies the opcode table by removing incorrect instruction forms.
- • Removes the possibility of users incorrectly specifying a rounding mode for these instructions.
- series_id
- binutils:risc-v: drop fcvt.q.l{,u} forms with rounding mode operand
- series_role
- reply
- series_parts
- []
- tags
-
- • binutils
- • risc-v
- • floating-point
- • assembler
- • opcode
- bugzilla_url
- —
- date
- 2026-07-24T00:00:00.000Z
[PATCH v4 04/12] RISC-V: drop FCVT.Q.L{,U} forms with rounding mode operand
This patch removes redundant forms of the RISC-V FCVT.Q.L and FCVT.Q.LU instructions from the assembler’s opcode table. These forms incorrectly allowed a floating-point rounding mode operand, which is not applicable to these specific conversions. The removal simplifies the opcode definitions and prevents incorrect instruction usage.