[PATCH v4 05/12] RISC-V: make FP rounding mode an optional operand
Project / Subsystem
binutils / risc-v
Date
2026-07-24
Proposer
Jan Beulich <jbeulich@suse.com>
Source type
public_inbox
Consensus
Proposed
Sentiment
—/10
Technical tradeoffs
- • Reduces opcode table size and complexity by making the rounding mode optional.
- • Introduces slightly more complex parsing logic in the assembler to handle optional operands.
All attributes
- project
- binutils
- subsystem
- risc-v
- patch_id
- —
- discussion_id
- 34185d40-e19d-48e3-a6a5-f48ef4a54ebd@suse.com
- source_type
- public_inbox
- title
- [PATCH v4 05/12] RISC-V: make FP rounding mode an optional operand
- headline
- RISC-V: make FP rounding mode an optional operand
- tldr
- Allow optional FP rounding mode operand for RISC-V instructions.
- proposer
- Jan Beulich <jbeulich@suse.com>
- consensus
- Proposed
- outcome
- proposed
- sentiment_score
- —
- technical_tradeoffs
-
- • Reduces opcode table size and complexity by making the rounding mode optional.
- • Introduces slightly more complex parsing logic in the assembler to handle optional operands.
- series_id
- binutils:risc-v: make fp rounding mode an optional operand
- series_role
- reply
- series_parts
- []
- tags
-
- • binutils
- • risc-v
- • floating-point
- • assembler
- • opcode
- bugzilla_url
- —
- date
- 2026-07-24T00:00:00.000Z
[PATCH v4 05/12] RISC-V: make FP rounding mode an optional operand
This patch modifies the RISC-V assembler to make the floating-point rounding mode operand optional for most instructions. This change simplifies the opcode table by reducing redundant entries and aligns the handling with similar ARM Vm and VM counterparts. The rounding mode is now implicitly handled unless explicitly specified, with an exception for FCVTMOD.W.D where ‘M’ is still required.