[PATCH v2 2/2] x86: ACE_V1 support for ACE-specific instructions
Project / Subsystem
binutils / x86
Date
2026-09-05
Proposer
Rohan Shenoy <RohanRadhesh.Shenoy@amd.com>
Source type
public_inbox
Consensus
Proposed
Sentiment
—/10
All attributes
- project
- binutils
- subsystem
- x86
- patch_id
- —
- discussion_id
- cde123df6ce754214c7482a3bc3ba109f807f63a.1788591257.git.RohanRadhesh.Shenoy@amd.com
- source_type
- public_inbox
- title
- [PATCH v2 2/2] x86: ACE_V1 support for ACE-specific instructions
- headline
- x86: ACE_V1 support for ACE-specific instructions
- tldr
- Adds assembler and disassembler support for new ACE_V1 specific instructions, including block scale register operations and tile outer products.
- proposer
- Rohan Shenoy <RohanRadhesh.Shenoy@amd.com>
- consensus
- Proposed
- outcome
- proposed
- sentiment_score
- —
- technical_tradeoffs
- []
- series_id
- binutils:x86: ace_v1 support for ace-specific instructions
- series_role
- reply
- series_parts
- []
- tags
-
- • binutils
- • x86
- • ace
- • isa
- • assembler
- bugzilla_url
- —
- date
- 2026-09-05T00:00:00.000Z
[PATCH v2 2/2] x86: ACE_V1 support for ACE-specific instructions
This patch series extends binutils support for the ACE_V1 (AI Compute Extensions) ISA by adding assembler and disassembler logic for ACE-specific instructions. This includes operations involving the block scale register, tile move writes, and various outer product instructions, referencing the ACE v1.16.2 specification.