[PATCH v2 1/2] x86: ACE_V1 support for AMX-shared instructions
Project / Subsystem
binutils / x86
Date
2026-09-05
Proposer
Rohan Shenoy <RohanRadhesh.Shenoy@amd.com>
Source type
public_inbox
Consensus
Proposed
Sentiment
—/10
Technical tradeoffs
- • Reusing AMX instructions for ACE_V1 may simplify implementation but requires careful validation to ensure correct behavior across both contexts.
- • Adding EVEX.V' validation adds complexity but prevents incorrect instruction encodings.
All attributes
- project
- binutils
- subsystem
- x86
- patch_id
- —
- discussion_id
- 5b6c56cbfd1d14e67d31556d4c0de464aad4deaa.1788591257.git.RohanRadhesh.Shenoy@amd.com
- source_type
- public_inbox
- title
- [PATCH v2 1/2] x86: ACE_V1 support for AMX-shared instructions
- headline
- x86: ACE_V1 support for AMX-shared instructions
- tldr
- Enables ACE_V1 architecture support in binutils, reusing AMX instructions for tile management and operations.
- proposer
- Rohan Shenoy <RohanRadhesh.Shenoy@amd.com>
- consensus
- Proposed
- outcome
- proposed
- sentiment_score
- —
- technical_tradeoffs
-
- • Reusing AMX instructions for ACE_V1 may simplify implementation but requires careful validation to ensure correct behavior across both contexts.
- • Adding EVEX.V' validation adds complexity but prevents incorrect instruction encodings.
- series_id
- binutils:x86: ace_v1 support for amx-shared instructions
- series_role
- reply
- series_parts
- []
- tags
-
- • binutils
- • x86
- • ace
- • amx
- • isa
- bugzilla_url
- —
- date
- 2026-09-05T00:00:00.000Z
[PATCH v2 1/2] x86: ACE_V1 support for AMX-shared instructions
This patch introduces assembler and disassembler support for the ACE_V1 architecture in binutils, enabling its use alongside existing AMX-shared instructions. It allows TMM register usage and includes validation for EVEX.V’ encoding to reject invalid combinations, ensuring correct interpretation of these AI-focused instructions.