[PATCH v2 0/2] x86: add ACE_V1 ISA support

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Project / Subsystem

binutils / x86

Date

2026-09-05

Proposer

Rohan Shenoy <RohanRadhesh.Shenoy@amd.com>

Source type

public_inbox

Consensus

Proposed

Sentiment

—/10

Technical tradeoffs

• Balancing reuse of existing AMX logic with the need for ACE-specific validation and instructions.
• Ensuring correct and safe handling of the EVEX prefix, particularly the EVEX.V' bit, for ACE instructions.

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All attributes

project: binutils
subsystem: x86
patch_id: —
discussion_id: cover.1788591257.git.RohanRadhesh.Shenoy@amd.com
source_type: public_inbox
title: [PATCH v2 0/2] x86: add ACE_V1 ISA support
headline: x86: add ACE_V1 ISA support
tldr: Adds assembler and disassembler support for the ACE_V1 ISA, enabling AI-focused instructions on x86.
proposer: Rohan Shenoy <RohanRadhesh.Shenoy@amd.com>
consensus: Proposed
outcome: proposed
sentiment_score: —
technical_tradeoffs: • Balancing reuse of existing AMX logic with the need for ACE-specific validation and instructions.
• Ensuring correct and safe handling of the EVEX prefix, particularly the EVEX.V' bit, for ACE instructions.
series_id: binutils:x86: add ace_v1 isa support
series_role: cover
series_parts: []
tags: • binutils
• x86
• ace
• isa
• assembler
url: https://inbox.sourceware.org/binutils/cover.1788591257.git.RohanRadhesh.Shenoy@amd.com
bugzilla_url: —
date: 2026-09-05T00:00:00.000Z

[PATCH v2 0/2] x86: add ACE_V1 ISA support

This patch series introduces support for the ACE (AI Compute Extensions) V1 ISA in binutils, covering both assembler and disassembler functionalities. The series is divided into two parts: the first enables ACE_V1 and supports AMX-shared instructions, while the second adds ACE-specific instructions. Revisions in V2 address feedback, refine table lookups, and add crucial EVEX.V’ validation for instruction encoding.