[PATCH] AArch64: Optimize short-range ADRP/ADD sequences
Project / Subsystem
binutils / aarch64
Date
2026-09-15
Proposer
Sivan Shani <sivan.shani@arm.com>
Source type
public_inbox
Consensus
Proposed
Sentiment
—/10
Technical tradeoffs
- • Reduces code size by replacing two instructions with one.
- • May improve performance by reducing instruction count and improving locality.
- • Adds complexity to the linker's relaxation pass.
- • Ensures correctness by checking for matching symbols, addends, registers, and non-overlapping relocations.
All attributes
- project
- binutils
- subsystem
- aarch64
- patch_id
- —
- discussion_id
- 20260915163722.96043-1-sivan.shani@arm.com
- source_type
- public_inbox
- title
- [PATCH] AArch64: Optimize short-range ADRP/ADD sequences
- headline
- AArch64: Optimize short-range ADRP/ADD sequences
- tldr
- Optimizes AArch64 ADRP/ADD sequences by relaxing them into NOP/ADR when possible.
- proposer
- Sivan Shani <sivan.shani@arm.com>
- consensus
- Proposed
- outcome
- proposed
- sentiment_score
- —
- technical_tradeoffs
-
- • Reduces code size by replacing two instructions with one.
- • May improve performance by reducing instruction count and improving locality.
- • Adds complexity to the linker's relaxation pass.
- • Ensures correctness by checking for matching symbols, addends, registers, and non-overlapping relocations.
- series_id
- —
- series_role
- standalone
- series_parts
- []
- tags
-
- • binutils
- • aarch64
- • optimization
- • linker
- • performance
- bugzilla_url
- —
- date
- 2026-09-15T00:00:00.000Z
[PATCH] AArch64: Optimize short-range ADRP/ADD sequences
This patch introduces an optimization for the AArch64 architecture in binutils’ linker. It identifies pairs of ADRP and ADD instructions used for generating addresses within a short range. If the target address fits within the range of a single ADR instruction, the sequence is transformed into a NOP and an ADR instruction. The patch includes checks for matching symbols, addends, and registers, rejects overlapping relocations, and preserves relocation information for --emit-relocs. New tests are added for various scenarios including different instruction set variants (LP64, ILP32) and relax modes.