[PATCH v4 4/7] x86: ACE V1 support for AMX-shared instructions
Project / Subsystem
binutils / x86
Date
2026-09-29
Proposer
Rohan Shenoy <RohanRadhesh.Shenoy@amd.com>
Source type
public_inbox
Consensus
Proposed
Sentiment
—/10
Technical tradeoffs
- • Reuses existing AMX code, simplifying ACE V1 integration.
- • Expands the scope of AMX-shared instructions to include ACE V1.
All attributes
- project
- binutils
- subsystem
- x86
- patch_id
- —
- discussion_id
- f330ab714f3d252cf3971323449f8a4da149b289.1790705096.git.RohanRadhesh.Shenoy@amd.com
- source_type
- public_inbox
- title
- [PATCH v4 4/7] x86: ACE V1 support for AMX-shared instructions
- headline
- x86: ACE V1 support for AMX-shared instructions
- tldr
- Enables ACE V1 architecture to reuse existing AMX instructions for tile management, row moves, and row converts.
- proposer
- Rohan Shenoy <RohanRadhesh.Shenoy@amd.com>
- consensus
- Proposed
- outcome
- proposed
- sentiment_score
- —
- technical_tradeoffs
-
- • Reuses existing AMX code, simplifying ACE V1 integration.
- • Expands the scope of AMX-shared instructions to include ACE V1.
- series_id
- binutils:x86: ace v1 support for amx-shared instructions
- series_role
- reply
- series_parts
- []
- tags
-
- • x86
- • ACE
- • AMX
- • tile instructions
- bugzilla_url
- —
- date
- 2026-09-29T00:00:00.000Z
[PATCH v4 4/7] x86: ACE V1 support for AMX-shared instructions
This patch enables the ACE V1 architecture and allows it to reuse existing AMX-shared instructions for tile management, row moves, and row converts. It also permits the usage of TMM registers under the ACE_V1 architecture, aligning with the ACE specification.