[PATCH v4 0/7] x86: add ACE V1 ISA support
Project / Subsystem
binutils / x86
Date
2026-09-29
Proposer
Rohan Shenoy <RohanRadhesh.Shenoy@amd.com>
Source type
public_inbox
Consensus
Proposed
Sentiment
—/10
Technical tradeoffs
- • Adds a significant new instruction set extension to binutils.
- • Requires multiple patches to introduce dependencies and the final support.
- • Balances code reuse (AMX) with new feature implementation.
All attributes
- project
- binutils
- subsystem
- x86
- patch_id
- —
- discussion_id
- cover.1790705096.git.RohanRadhesh.Shenoy@amd.com
- source_type
- public_inbox
- title
- [PATCH v4 0/7] x86: add ACE V1 ISA support
- headline
- x86: add ACE V1 ISA support
- tldr
- Adds assembler and disassembler support for the x86 ACE V1 (AI Compute Extensions) instructions.
- proposer
- Rohan Shenoy <RohanRadhesh.Shenoy@amd.com>
- consensus
- Proposed
- outcome
- proposed
- sentiment_score
- —
- technical_tradeoffs
-
- • Adds a significant new instruction set extension to binutils.
- • Requires multiple patches to introduce dependencies and the final support.
- • Balances code reuse (AMX) with new feature implementation.
- series_id
- binutils:x86: add ace v1 isa support
- series_role
- cover
- series_parts
- []
- tags
-
- • x86
- • ACE
- • assembler
- • disassembler
- • instruction set
- bugzilla_url
- —
- date
- 2026-09-29T00:00:00.000Z
[PATCH v4 0/7] x86: add ACE V1 ISA support
This patch series introduces assembler and disassembler support for the new x86 ACE V1 (AI Compute Extensions) instructions. The series first adds prerequisite patches for internal features like ‘TILE’ and EVEX decoding, then enables ACE V1 and adds support for its specific instructions, including block scale registers and tile operations.