[PATCH v4 7/7] x86: add ACE V1 tile outer product instructions
Project / Subsystem
binutils / x86
Date
2026-09-29
Proposer
Rohan Shenoy <RohanRadhesh.Shenoy@amd.com>
Source type
public_inbox
Consensus
Proposed
Sentiment
—/10
Technical tradeoffs
- • Adding support for new instruction sets requires extensive modifications to opcode tables and disassembler logic, increasing maintenance overhead.
- • The use of EVEX encoding for these instructions necessitates careful handling of prefix bytes and register specifiers to ensure correct assembly and disassembly.
All attributes
- project
- binutils
- subsystem
- x86
- patch_id
- —
- discussion_id
- 521814471f9493bdab4ff0a646bebfcd2e7d8ee9.1790705096.git.RohanRadhesh.Shenoy@amd.com
- source_type
- public_inbox
- title
- [PATCH v4 7/7] x86: add ACE V1 tile outer product instructions
- headline
- x86: add ACE V1 tile outer product instructions
- tldr
- Adds assembler and disassembler support for ACE V1 tile outer product instructions.
- proposer
- Rohan Shenoy <RohanRadhesh.Shenoy@amd.com>
- consensus
- Proposed
- outcome
- proposed
- sentiment_score
- —
- technical_tradeoffs
-
- • Adding support for new instruction sets requires extensive modifications to opcode tables and disassembler logic, increasing maintenance overhead.
- • The use of EVEX encoding for these instructions necessitates careful handling of prefix bytes and register specifiers to ensure correct assembly and disassembly.
- series_id
- binutils:x86: add ace v1 tile outer product instructions
- series_role
- reply
- series_parts
- []
- tags
-
- • x86
- • ace
- • amx
- • assembler
- • disassembler
- bugzilla_url
- —
- date
- 2026-09-29T00:00:00.000Z
[PATCH v4 7/7] x86: add ACE V1 tile outer product instructions
This patch enhances binutils by adding assembler and disassembler support for several x86 ACE V1 tile outer product instructions: TOP2BF16PS, TOP4B*, and TOP4MX*. The changes include updates to the NEWS file, test suites, and various opcode and disassembler-related header files. This brings comprehensive support for these advanced matrix operations to the toolchain.