Re: [PATCH] x86-64: Use UD0/UD2 after indirect jump in PLT entries
Project / Subsystem
binutils / x86-64
Date
2026-10-02
Proposer
H.J. Lu <h.lu@intel.com>
Source type
public_inbox
Consensus
Under Review
Sentiment
—/10
Technical tradeoffs
- • Using UD0/UD2 might be less performant or less secure if they don't act as true speculation barriers.
- • Using LFENCE or INT3 might introduce performance overhead if they are not strictly necessary for all indirect jumps.
- • Correctly identifying indirect jumps that benefit from speculation barriers is crucial.
All attributes
- project
- binutils
- subsystem
- x86-64
- patch_id
- —
- discussion_id
- CAKSQd8UDfv+umXcmkb-a0d3COGYkn+bizrkqWqfW42FqcDMahQ@mail.gmail.com
- source_type
- public_inbox
- title
- Re: [PATCH] x86-64: Use UD0/UD2 after indirect jump in PLT entries
- headline
- x86-64: Use UD0/UD2 after indirect jump in PLT entries
- tldr
- Discussion on using UD0/UD2 versus LFENCE/INT3 as speculation barriers after indirect jumps in PLT entries.
- proposer
- H.J. Lu <h.lu@intel.com>
- consensus
- Under Review
- outcome
- under_review
- sentiment_score
- —
- technical_tradeoffs
-
- • Using UD0/UD2 might be less performant or less secure if they don't act as true speculation barriers.
- • Using LFENCE or INT3 might introduce performance overhead if they are not strictly necessary for all indirect jumps.
- • Correctly identifying indirect jumps that benefit from speculation barriers is crucial.
- series_id
- —
- series_role
- reply
- series_parts
- []
- tags
-
- • x86-64
- • binutils
- • speculation
- • optimization
- • PLT
- bugzilla_url
- —
- date
- 2026-10-02T00:00:00.000Z
Re: [PATCH] x86-64: Use UD0/UD2 after indirect jump in PLT entries
This thread discusses the effectiveness of using UD0/UD2 instructions as speculation barriers following indirect jumps in PLT entries, as proposed in a related patch. Christian Ludloff argues that UD0/UD2 are not guaranteed speculation barriers according to Intel’s SDM, which recommends LFENCE or INT3 instead. The participants debate the nuances of CPU speculation and exception handling as barriers.