Landing: 0c84051bd679

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Project / Subsystem

gcc / aarch64

Date

2025-11-25

Author

Karl Meakin

Commit

0c84051bd679d0060b0e8832463672b914b8f1ab

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: aarch64
patch_id: —
commit_hash: 0c84051bd679d0060b0e8832463672b914b8f1ab
source_type: github
headline: aarch64: Correct comments for SVE/ASIMD/FP register constraints
tldr: Clarifies register constraint comments for aarch64 to include SVE registers.
author: Karl Meakin
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • aarch64
• SVE
• documentation
• ARM
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/0c84051bd679d0060b0e8832463672b914b8f1ab
date: 2025-11-25T00:00:00.000Z

Comments for the ‘w’, ‘x’, and ‘y’ register constraints in the aarch64 backend have been corrected. They now accurately reflect that these constraints apply to SVE (Scalable Vector Extension) registers in addition to Advanced SIMD and Floating-Point registers.