Landing: 52d5a8870d21

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Project / Subsystem

gcc / aarch64/sve

Date

2025-12-22

Author

Artemiy Volkov

Commit

52d5a8870d2108c660c34c8c1b7ea255809817d5

Source

github

Perf win

Yes

Breaking

View on GitHub →

All attributes

project: gcc
subsystem: aarch64/sve
patch_id: —
commit_hash: 52d5a8870d2108c660c34c8c1b7ea255809817d5
source_type: github
headline: AArch64 SVE now combines AdvSIMD and SVE vector duplicates.
tldr: GCC now combines AdvSIMD and SVE vector duplicates into a single instruction for AArch64, improving code generation.
author: Artemiy Volkov
outcome: committed
performance_win: true
breaking_change: false
series_id: —
series_parts: []
tags: • aarch64
• sve
• vectorization
• optimization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/52d5a8870d2108c660c34c8c1b7ea255809817d5
date: 2025-12-22T00:00:00.000Z

The compiler previously used an intermediate 128-bit AdvSIMD register when duplicating a 64-bit or narrower value into an SVE register. This change adds a pattern that combine can use to merge two vec_duplicate instructions (scalar -> AdvSIMD and AdvSIMD -> SVE) into a single one (scalar -> SVE). This results in more efficient code generation, reducing the number of instructions needed.