Landing: be498c1e1356

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Project / Subsystem

gcc / aarch64

Date

2025-12-31

Author

Artemiy Volkov

Commit

be498c1e13560ef029df20ee96471ec66eaad000

Source

github

Perf win

Yes

Breaking

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All attributes

project: gcc
subsystem: aarch64
patch_id: —
commit_hash: be498c1e13560ef029df20ee96471ec66eaad000
source_type: github
headline: AArch64: Add zeroing forms for predicated SVE integer extends
tldr: GCC now supports zeroing predication for SVE integer extension instructions on AArch64, improving code generation for SVE2.2 and SME2.2.
author: Artemiy Volkov
outcome: committed
performance_win: true
breaking_change: false
series_id: —
series_parts: []
tags: • aarch64
• sve
• sve2.2
• sme2.2
• code generation
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/be498c1e13560ef029df20ee96471ec66eaad000
date: 2025-12-31T00:00:00.000Z

This commit adds support for zeroing predication to SVE integer extension instructions (SXTB, SXTH, SXTW, UXTB, UXTH, UXTW) for AArch64. This feature, available in SVE2.2 and SME2.2, allows the generation of a single zeroing-predication form of these instructions when merging with an independent value. The change modifies patterns in aarch64-sve.md and adds new tests to verify the codegen for the new zeroing variants.