Landing: 690c6055daa8

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Project / Subsystem

gcc / aarch64

Date

2026-01-09

Author

Artemiy Volkov

Commit

690c6055daa818629426d0f4dc6debd96ef20a36

Source

github

Perf win

Yes

Breaking

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All attributes

project: gcc
subsystem: aarch64
patch_id: —
commit_hash: 690c6055daa818629426d0f4dc6debd96ef20a36
source_type: github
headline: AArch64: Add zeroing forms for predicated SVE integer unary operations
tldr: GCC now supports zeroing predication for SVE integer unary operations on AArch64, leveraging SVE2.2 and SME2.2 for optimized code generation.
author: Artemiy Volkov
outcome: committed
performance_win: true
breaking_change: false
series_id: —
series_parts: []
tags: • aarch64
• sve
• sve2.2
• sme2.2
• code generation
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/690c6055daa818629426d0f4dc6debd96ef20a36
date: 2026-01-09T00:00:00.000Z

This commit introduces support for zeroing predication in SVE integer unary operations (ABS, CLS, CLZ, CNT, CNOT, NEG, NOT, RBIT, SQABS, SQNEG, URECPE, URSRQTE) on AArch64 processors. Enabled by SVE2.2 and SME2.2, this change adds new alternatives to aarch64-sve.md and aarch64-sve2.md, emitting zeroing-predication forms when a const_vector of all zeroes acts as the merge operand. New tests have been added to validate the codegen for these zeroing variants.