Landing: a5e5f1f19e54
Project / Subsystem
gcc / gcc/aarch64
Date
2026-01-09
Author
Artemiy Volkov
Commit
a5e5f1f19e545f92e962cd62cef3c79825e8eecf
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc/aarch64
- patch_id
- —
- commit_hash
- a5e5f1f19e545f92e962cd62cef3c79825e8eecf
- source_type
- github
- headline
- AArch64: Add zeroing forms for predicated SVE bit reversal operations
- tldr
- The compiler now supports zeroing predication for SVE bit reversal operations under SVE2.2 or SME2.2.
- author
- Artemiy Volkov
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • aarch64
- • sve
- • sme
- • intrinsics
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-01-09T00:00:00.000Z
The compiler now supports zeroing predication for SVE bit reversal operations under SVE2.2 or SME2.2. This change adds an alternative for the zeroing-predication forms of the original instructions. The pattern for REVD also required changes to the predicate for operand 3 to accept constant zero RTX whenever SVE2.2 is enabled, and uses the /z form of the REVD instruction for PRED_X predication to save a data dependency.