Landing: e637c95d4fba

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Project / Subsystem

gcc / risc-v

Date

2026-03-27

Author

Robin Dapp

Commit

e637c95d4fbabac758a22247462d8b61ec3685a4

Source

github

Perf win

Yes

Breaking

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: e637c95d4fbabac758a22247462d8b61ec3685a4
source_type: github
headline: RISC-V: Use more whole-register loads and stores.
tldr: The RISC-V backend can now emit more whole-register loads and stores, improving code generation by allowing more flexible vsetvl placement.
author: Robin Dapp
outcome: committed
performance_win: true
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• vectorization
• optimization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/e637c95d4fbabac758a22247462d8b61ec3685a4
date: 2026-03-27T00:00:00.000Z

The RISC-V backend can now split off whole-register loads and stores from pred_mov operations. Using whole-register operations avoids the need for a vtype and provides more freedom in placing vsetvl instructions. This optimization should lead to better code generation for RISC-V vector code.