Landing: 36f0b74a8313
Project / Subsystem
gcc / gcc
Date
2026-04-25
Author
Jeff Law
Commit
36f0b74a8313d2f16a931451415ad8b306268acf
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc
- patch_id
- —
- commit_hash
- 36f0b74a8313d2f16a931451415ad8b306268acf
- source_type
- github
- headline
- Improve code generation for RISC-V shifts with constant counts
- tldr
- GCC now generates better code for RISC-V shifts with a constant count derived from a subtraction, such as ``31 - n``, by using the bitwise NOT operation.
- author
- Jeff Law
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • optimization
- • code generation
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-04-25T00:00:00.000Z
GCC now uses the bitwise NOT operation instead of subtraction when generating code for RISC-V shifts where the shift count is expressed as 31 - n or 63 - n. This optimization avoids loading the constant (31 or 63) into a register, resulting in more compact code. The optimization is enabled when the processor implements SHIFT_COUNT_TRUNCATED semantics, meaning that only the lower bits of the shift count are relevant.