Landing: 5385c9588b1a

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Project / Subsystem

gcc / gcc

Date

2026-04-25

Author

Jeff Law

Commit

5385c9588b1a76cbba5e42443673681f033c5d77

Source

github

Perf win

Yes

Breaking

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All attributes

project: gcc
subsystem: gcc
patch_id: —
commit_hash: 5385c9588b1a76cbba5e42443673681f033c5d77
source_type: github
headline: Improve bit masking of shifted values
tldr: GCC on RISC-V now optimizes bit masking operations on shifted values, potentially reducing code size and improving performance.
author: Jeff Law
outcome: committed
performance_win: true
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• optimization
• bit manipulation
• code generation
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/5385c9588b1a76cbba5e42443673681f033c5d77
date: 2026-04-25T00:00:00.000Z

The RISC-V backend in GCC can now generate more efficient code for certain bit masking operations applied to shifted values. When both upper and lower bits are masked off, and the input value is already shifted, GCC can use a shift triplet or just two shifts, reducing instruction count. This optimization improves code density and potentially enhances performance in code that uses bit manipulation.