Landing: 1e4294de8ef6
Project / Subsystem
gcc / gcc
Date
2026-04-28
Author
Jeff Law
Commit
1e4294de8ef6d606b61d7d4b2b8b6237651961c5
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc
- patch_id
- —
- commit_hash
- 1e4294de8ef6d606b61d7d4b2b8b6237651961c5
- source_type
- github
- headline
- Improve equality test of sign bit splat against zero
- tldr
- GCC now optimizes equality tests on RISC-V by converting sign bit splats against zero into simpler less-than/greater-than-or-equal tests.
- author
- Jeff Law
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • optimization
- • code generation
- • tree-optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-04-28T00:00:00.000Z
This commit improves code generation for RISC-V, specifically targeting equality tests of sign bit splats against zero. By converting these tests into simpler less-than or greater-than-or-equal tests, the compiler avoids the need for sign bit splat operations, resulting in more efficient code. The change primarily affects RV64 due to how subregisters are handled, and a new test case verifies the optimization on both RV32 and RV64.