Landing: 6495ab914092
Project / Subsystem
gcc / gcc
Date
2026-04-28
Author
Jeff Law
Commit
6495ab91409202a218b4e12979e9d7c9fd8fabdb
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc
- patch_id
- —
- commit_hash
- 6495ab91409202a218b4e12979e9d7c9fd8fabdb
- source_type
- github
- headline
- Enable RISC-V to generate shNadd instructions.
- tldr
- Improve RISC-V code generation by promoting intermediate operations from SI to DI, enabling the use of shNadd instructions.
- author
- Jeff Law
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • code generation
- • optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-04-28T00:00:00.000Z
This change promotes intermediate operations from SI (single-precision integer) to DI (double-precision integer) in certain RISC-V code patterns. This enables the generation of shNadd instructions, which combine a shift and addition, resulting in more efficient code. The patch includes a new test case and has been tested on various RISC-V configurations.