Landing: da9fe0aafb08

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Project / Subsystem

gcc / gcc

Date

2026-04-28

Author

Richard Biener

Commit

da9fe0aafb08d4feeffcd2ac5782187b51a75912

Source

github

Perf win

Yes

Breaking

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All attributes

project: gcc
subsystem: gcc
patch_id: —
commit_hash: da9fe0aafb08d4feeffcd2ac5782187b51a75912
source_type: github
headline: Enable AVX-512 epilogue optimisations for ZNVER6.
tldr: The compiler can now use AVX-512 optimisations that avoid zeroing registers at function ends on AMD Zenver6 CPUs.
author: Richard Biener
outcome: committed
performance_win: true
breaking_change: false
series_id: —
series_parts: []
tags: • gcc
• x86
• avx-512
• optimization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/da9fe0aafb08d4feeffcd2ac5782187b51a75912
date: 2026-04-28T00:00:00.000Z

The AVX-512 masked and two-epilogue optimisations were enabled for the upcoming AMD Zenver6 core, which allows the compiler to generate more efficient code when using AVX-512 intrinsics, especially at the end of functions where registers need to be cleared. This can result in smaller code size and faster execution times for AVX-512 heavy workloads.