Landing: 8add8bccdcdd

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Project / Subsystem

gcc / risc-v

Date

2026-04-30

Author

wangzicong

Commit

8add8bccdcdd40103c320648d00a07c54d97160d

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: 8add8bccdcdd40103c320648d00a07c54d97160d
source_type: github
headline: RISC-V: Prevent tuple vector modes from tying to non-tuple modes.
tldr: Fixes type conversions when using RISC-V vector intrinsics with the zvl extension by preventing tuple vector modes from being tieable to non-tuple modes.
author: wangzicong
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• vectorization
• type conversion
• zvl
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/8add8bccdcdd40103c320648d00a07c54d97160d
date: 2026-04-30T00:00:00.000Z

This change prevents the RISC-V backend from incorrectly converting between tuple and non-tuple vector modes when the zvl extension is enabled. Without this fix, extracting an inner vector mode from a tuple could result in an unexpected conversion to a non-tuple mode (e.g., RVVMF2HI converted to DI, rather than RVVM1QI). This ensures that vector types are handled correctly during compilation, avoiding unexpected behavior and potential errors when using RISC-V vector instructions.