Landing: 1fb066c160ca
Project / Subsystem
gcc / risc-v
Date
2026-05-01
Author
Jin Ma
Commit
1fb066c160cab48d141241494a24a6f2957be368
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 1fb066c160cab48d141241494a24a6f2957be368
- source_type
- github
- headline
- Fix Missing Braces in riscv_rtx_costs for slli.uw Pattern
- tldr
- Fixes a RISC-V code generation issue where an AND case lacked braces, leading to incorrect cost calculations and potentially skipping other pattern checks.
- author
- Jin Ma
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • code generation
- • bugfix
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-05-01T00:00:00.000Z
This commit fixes a code generation issue in the RISC-V backend related to the slli.uw instruction pattern. The absence of braces in an AND case within the riscv_rtx_costs function resulted in premature termination of cost calculations. This caused the compiler to potentially skip subsequent pattern checks and fallthrough cases, affecting code generation for AND+ASHIFT combinations when specific conditions are met (TARGET_ZBA, TARGET_64BIT, and DImode).