Landing: 174009941a78
Project / Subsystem
gcc / gcc
Date
2026-05-02
Author
Jeff Law
Commit
174009941a788048084a32204aca26bec3b75298
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc
- patch_id
- —
- commit_hash
- 174009941a788048084a32204aca26bec3b75298
- source_type
- github
- headline
- RISC-V: Optimize shift+rotate sequences to simple shift instructions.
- tldr
- The RISC-V backend now optimizes specific shift and rotate sequences into a single shift instruction, improving code generation for bit manipulation.
- author
- Jeff Law
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • optimization
- • bit manipulation
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-05-02T00:00:00.000Z
The RISC-V backend now recognizes specific sequences of shifts and rotates with masking as a single shift instruction. This optimization applies when the shifts clear the upper bits and the rotate operates on the lower bits, with a consecutive run of set bits in the mask including bits 31..63. This reduces a 3-instruction sequence to a single slliw instruction, improving code density and potentially performance for bit manipulation operations. This addresses PR target/109038.