Landing: 21d6148cf38c

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Project / Subsystem

gcc / risc-v

Date

2026-05-06

Author

Zhongyao Chen

Commit

21d6148cf38c6aaafaa616b7c153ace35c174971

Source

github

Perf win

Yes

Breaking

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: 21d6148cf38c6aaafaa616b7c153ace35c174971
source_type: github
headline: RISC-V: Scale vector operation costs by LMUL for latency and register pressure.
tldr: The RISC-V backend now accounts for the increased cost of larger LMULs in vector operations, which should improve code generation.
author: Zhongyao Chen
outcome: committed
performance_win: true
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• vectorization
• cost model
• optimization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/21d6148cf38c6aaafaa616b7c153ace35c174971
date: 2026-05-06T00:00:00.000Z

This patch introduces multiplicative cost scaling (x2/x4/x8) to better model the increased latency and register pressure associated with larger LMULs (Lane Multiplier) in RISC-V vector operations. The scaling is applied uniformly in the adjust_stmt_cost function for all vector statements. This change intends to improve the accuracy of cost modeling and thus enable better optimization decisions during code generation.