Landing: 0200c300bd8b

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Project / Subsystem

gcc / gcc

Date

2026-05-07

Author

Jeff Law

Commit

0200c300bd8b0d364c885637482a10cb9467580c

Source

github

Perf win

Yes

Breaking

View on GitHub →

All attributes

project: gcc
subsystem: gcc
patch_id: —
commit_hash: 0200c300bd8b0d364c885637482a10cb9467580c
source_type: github
headline: Improve code for (1 << N) & 0x1 on RISC-V.
tldr: A RISC-V-specific code splitter improves the generated assembly for the expression (1 << N) & 0x1.
author: Jeff Law
outcome: committed
performance_win: true
breaking_change: false
series_id: —
series_parts: []
tags: • RISC-V
• optimization
• code generation
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/0200c300bd8b0d364c885637482a10cb9467580c
date: 2026-05-07T00:00:00.000Z

The RISC-V backend now generates more efficient code for expressions of the form (1 << N) & 0x1 on RV64. A new code splitter handles the case of a 32-bit shift on RV64. The optimization masks the shift count to sanitize it, generating two instructions: andi and seqz instead of li, sllw, and andi.