Landing: 046bc3484c90
Project / Subsystem
gcc / gcc
Date
2026-05-08
Author
Jeff Law
Commit
046bc3484c90a25fb09c851d6afac13b790bb20c
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc
- patch_id
- —
- commit_hash
- 046bc3484c90a25fb09c851d6afac13b790bb20c
- source_type
- github
- headline
- RISC-V: Utilize slliw instruction for left shifted signed bitfield extractions.
- tldr
- RISC-V code generation now uses `slliw` instruction to optimize left-shifted signed bitfield extractions, improving performance in specific scenarios.
- author
- Jeff Law
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • optimization
- • code generation
- • bitfield
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-05-08T00:00:00.000Z
This commit optimizes RISC-V code generation by using the slliw instruction for certain left-shifted signed bitfield extractions. This eliminates the need for separate sign extension instructions, resulting in more compact and efficient code. The optimization is specifically applied when extracting a sign-extended bitfield of size N, left-shifting it by M bits, and masking the result using AND, where N+M equals 32. This optimization improves performance in cases like the random number generator.