Landing: bb0cbdac1969
Project / Subsystem
gcc / xtensa
Date
2026-05-08
Author
Takayuki 'January June' Suwa
Commit
bb0cbdac196986de933f4f93097de021c3686d7c
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- xtensa
- patch_id
- —
- commit_hash
- bb0cbdac196986de933f4f93097de021c3686d7c
- source_type
- github
- headline
- Xtensa: Define HONOR_REG_ALLOC_ORDER as 1
- tldr
- This commit disables incorrect register save cost estimation in function prologues/epilogues for Xtensa, potentially reducing stack frame usage.
- author
- Takayuki 'January June' Suwa
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • xtensa
- • register allocation
- • optimization
- • stack frame
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-05-08T00:00:00.000Z
The Xtensa ISA was allocating slightly more function stack frames after a previous patch related to IRA (Interprocedural Register Allocation). This commit disables the incorrect register save cost estimation in function prologues/epilogues by defining the HONOR_REG_ALLOC_ORDER macro as 1. This can reduce stack frame usage, especially when using the CALL0 ABI.