Landing: aac8c3738bb2

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Project / Subsystem

gcc / riscv

Date

2026-05-15

Author

Xi Ruoyao

Commit

aac8c3738bb26b72281e55778428af559c9bb032

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: riscv
patch_id: —
commit_hash: aac8c3738bb26b72281e55778428af559c9bb032
source_type: github
headline: Fixes SSP assembly generation with xtheadmemidx extension in RISC-V.
tldr: Fixes stack smashing protection (SSP) assembly generation for RISC-V when the xtheadmemidx extension is enabled, using correct move instructions.
author: Xi Ruoyao
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • riscv
• security
• SSP
• xtheadmemidx
discussion_id_link: github:gcc-mirror/gcc#125320
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/aac8c3738bb26b72281e55778428af559c9bb032
date: 2026-05-15T00:00:00.000Z

When the RISC-V extension xtheadmemidx is enabled, the compiler needs to employ different instructions for stack smashing protection (SSP). The original code was hardcoding ld/sd instructions which are not suitable for all memory operands accepted by the m constraint. This commit replaces the hardcoded instructions with a call to riscv_output_move() to select the correct assembly template. This ensures that SSP works correctly with the xtheadmemidx extension.