Landing: 44a31df54837

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Project / Subsystem

gcc / aarch64

Date

2026-05-18

Author

Artemiy Volkov

Commit

44a31df54837adf2f7815e7966dfe8ac32eb8f3b

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: aarch64
patch_id: —
commit_hash: 44a31df54837adf2f7815e7966dfe8ac32eb8f3b
source_type: github
headline: AArch64 introduces partial AdvSIMD vector modes.
tldr: GCC now supports partial (16- and 32-bit) AdvSIMD vector modes on AArch64 for duplication into full-sized registers.
author: Artemiy Volkov
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • aarch64
• advsimd
• vectorization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/44a31df54837adf2f7815e7966dfe8ac32eb8f3b
date: 2026-05-18T00:00:00.000Z

This commit introduces new partial AdvSIMD vector modes (V4QI, V2QI, V2HI, and V2BF) for AArch64. These modes are intended for duplication into full-sized registers. The commit implements the “mov” expand and the “aarch64_simd_mov” instruction split for the new modes. It also adds aarch64_advsimd_sub_dword_mode_p to detect the new modes and disables vec_perm_const vectorization.