Landing: 900b5386f501
Project / Subsystem
gcc / gcc
Date
2026-05-18
Author
Jeff Law
Commit
900b5386f501f1b108959f93b0073842ebde3eea
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc
- patch_id
- —
- commit_hash
- 900b5386f501f1b108959f93b0073842ebde3eea
- source_type
- github
- headline
- Improve SI->DI zero/sign extension patterns for RISC-V
- tldr
- Improves code generation for zero-extension on RISC-V by using shift pairs when Zba/Zbb extensions are unavailable.
- author
- Jeff Law
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • optimization
- • code generation
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-05-18T00:00:00.000Z
This patch enhances zero-extension code generation for RISC-V, particularly when the Zba/Zbb extensions are not available. It generates shift pairs for REG operands instead of relying solely on define_insn_and_split, which is now used only for MEM sources. This change leads to better code in some cases and paves the way for further optimization improvements.