Landing: 5de5fd66196e
Project / Subsystem
gcc / risc-v
Date
2026-05-19
Author
Jin Ma
Commit
5de5fd66196e052c73375e80c1a232b2e1f36707
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 5de5fd66196e052c73375e80c1a232b2e1f36707
- source_type
- github
- headline
- RISC-V: Fix several bugs in macro fusion logic.
- tldr
- This patch fixes correctness and minor issues in the RISC-V macro fusion logic, including incorrect checks and typos.
- author
- Jin Ma
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • bugfix
- • optimization
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-05-19T00:00:00.000Z
Several correctness issues in the RISC-V macro fusion logic were fixed. An incorrect XINT access in RISCV_FUSE_AUIPC_LD was corrected to use SET_SRC (prev_set). The base register comparison in RISCV_FUSE_CACHE_ALIGNED_STD was corrected from != to ==. Redundant checks in RISCV_FUSE_B_ALUI and RISCV_FUSE_LDINDEXED were removed. A typo in a comment was fixed, and the dump output name for CACHE_ALIGNED_STD was corrected.