Landing: 06daaf8fad9e
Project / Subsystem
gcc / gcc
Date
2026-05-23
Author
Philipp Tomsich
Commit
06daaf8fad9e94a2c2399b1e7208c87a134711ed
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc
- patch_id
- —
- commit_hash
- 06daaf8fad9e94a2c2399b1e7208c87a134711ed
- source_type
- github
- headline
- Improve slli+zext+andi sequence for RISC-V
- tldr
- Improved RISC-V code generation by optimizing the slli+zext+andi sequence into slli+srli.
- author
- Philipp Tomsich
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • optimization
- • code generation
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-05-23T00:00:00.000Z
The compiler now optimizes the sequence slli+zext+andi into slli+srli for RISC-V architectures. This optimization reduces the number of instructions needed for certain address calculations, potentially improving performance. A new test case was added to verify the optimization. The change was tested on both RISC-V 32-bit and 64-bit configurations.