Landing: 34d9e6df85f8

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Project / Subsystem

gcc / risc-v

Date

2026-05-26

Author

Jin Ma

Commit

34d9e6df85f888c707c6b3b069ccfc6ea49efd56

Source

github

Perf win

Yes

Breaking

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project: gcc
subsystem: risc-v
patch_id: —
commit_hash: 34d9e6df85f888c707c6b3b069ccfc6ea49efd56
source_type: github
headline: RISC-V: Correct REGNO_REG_CLASS for FP hard registers.
tldr: The REGNO_REG_CLASS macro now returns the correct register class for all floating-point registers, fixing a cost model corruption in IRA.
author: Jin Ma
outcome: committed
performance_win: true
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• register allocation
• code generation
• bugfix
• optimization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/34d9e6df85f888c707c6b3b069ccfc6ea49efd56
date: 2026-05-26T00:00:00.000Z

The REGNO_REG_CLASS macro in the RISC-V backend now returns the minimal register class containing each FP hard register. Previously, some FP registers were incorrectly mapped to RVC_FP_REGS, corrupting IRA’s cost model and leading to suboptimal register allocation. This fix ensures that the cost model accurately reflects the cost of using each register, which can lead to better code generation.