Landing: a6ee91793b9f

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Project / Subsystem

gcc / aarch64

Date

2026-05-27

Author

Tamar Christina

Commit

a6ee91793b9f4d28ccd3fcc6f607f646d305a39e

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: aarch64
patch_id: —
commit_hash: a6ee91793b9f4d28ccd3fcc6f607f646d305a39e
source_type: github
headline: AArch64: Fix SVE to SIMD lowering optimization.
tldr: Corrects an SVE to SIMD lowering optimization bug that generated invalid code on AArch64.
author: Tamar Christina
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • aarch64
• SVE
• SIMD
• optimization
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/a6ee91793b9f4d28ccd3fcc6f607f646d305a39e
date: 2026-05-27T00:00:00.000Z

This patch fixes a bug in the SVE to SIMD lowering optimization for AArch64 architecture. The optimization, intended to convert SVE loads with known predicates into Adv. SIMD loads without predicates, was generating incorrect code due to scalar floating-point constants being created using vector broadcasting operations. The fix involves creating a full SVE vector of zeros and writing only the desired values using an INSR instruction, with patterns provided to optimize this process.