Landing: f3f8bb6afbcd

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Project / Subsystem

gcc / avr

Date

2026-05-28

Author

Georg-Johann Lay

Commit

f3f8bb6afbcdc8a9dc5e63343f2826492a448c79

Source

github

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Breaking

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All attributes

project: gcc
subsystem: avr
patch_id: —
commit_hash: f3f8bb6afbcdc8a9dc5e63343f2826492a448c79
source_type: github
headline: AVR: Use hard-reg constraints in divmod instructions.
tldr: The AVR backend now uses hard-register constraints for division and modulo operations, simplifying the instruction patterns.
author: Georg-Johann Lay
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • avr
• codegen
• instruction selection
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/f3f8bb6afbcdc8a9dc5e63343f2826492a448c79
date: 2026-05-28T00:00:00.000Z

This change replaces explicit hard-register specifications with hard-register constraints in the instruction patterns for division and modulo operations. This simplifies the code and removes unnecessary splitting functions for these operations. No user-visible impact is expected.