Landing: baa8b7246740
Project / Subsystem
gcc / gcc
Date
2026-05-31
Author
Jeff Law
Commit
baa8b724674018e568c571b2b610658d8dc0223d
Source
github
Perf win
Yes
Breaking
No
All attributes
- project
- gcc
- subsystem
- gcc
- patch_id
- —
- commit_hash
- baa8b724674018e568c571b2b610658d8dc0223d
- source_type
- github
- headline
- Improve code generation for select between register and -1 on RISC-V.
- tldr
- GCC now generates more compact RISC-V code for conditional assignments where one branch is -1.
- author
- Jeff Law
- outcome
- committed
- performance_win
- true
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • code generation
- • optimization
- • if-conversion
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-05-31T00:00:00.000Z
GCC now generates more compact code for conditional assignments where one branch assigns -1 to a register. The new sequence uses SLTI (set less than immediate) to generate 1 or 0, subtracts 1 to get 0 or -1, then ORs the result with the other input register. This reduces code size from 18 bytes to 10 bytes, which can improve performance on designs where instruction cache misses are costly. The improvement only applies to register,-1, and not const,-1 sequences.