Landing: 18adc749c657
Project / Subsystem
gcc / risc-v
Date
2026-06-03
Author
Kito Cheng
Commit
18adc749c657c8939634ef8554923e07c960ec24
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- risc-v
- patch_id
- —
- commit_hash
- 18adc749c657c8939634ef8554923e07c960ec24
- source_type
- github
- headline
- RISC-V canonical extension order now matches the latest ISA specification.
- tldr
- RISC-V extension canonical order is updated to align with the latest ISA specification, moving 'v' before 'p' and dropping 'n'.
- author
- Kito Cheng
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • isa
- • spec-compliance
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-06-03T00:00:00.000Z
The canonical order for RISC-V extensions has been updated to reflect recent adjustments in the RISC-V ISA manual. This change moves the ‘v’ (Vector) extension before ‘p’ (Packed-SIMD) and removes ‘n’ (User-level Interrupts) from the standard extension set. Although these extensions are not yet ratified, this update ensures GCC’s internal representation matches the evolving specification.