Landing: c0b97b859d18

Project / Subsystem

gcc / risc-v

Date

2026-06-09

Author

Monk Chiang

Commit

c0b97b859d18b56faaa3d55a617fe784185aa3e1

Source

github

Perf win

Breaking

All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: c0b97b859d18b56faaa3d55a617fe784185aa3e1
source_type: github
headline: RISC-V: Add load-to-address bypass for SiFive-7 series
tldr: RISC-V: Add load-to-address bypass for SiFive-7 series
author: Monk Chiang
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: []
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/c0b97b859d18b56faaa3d55a617fe784185aa3e1
date: 2026-06-09T00:00:00.000Z

Summary unavailable — see source link.