Landing: 988520330b92
Project / Subsystem
gcc / riscv
Date
2026-06-13
Author
panciyan@eswincomputing.com
Commit
988520330b92848548cc88a449db4cd5d9f5bcf1
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- riscv
- patch_id
- —
- commit_hash
- 988520330b92848548cc88a449db4cd5d9f5bcf1
- source_type
- github
- headline
- Fix data type iterator for RISC-V pack RS register
- tldr
- This commit corrects the data type iterator used in the RISC-V `pack` instruction definition within GCC to ensure proper matching of half a target word.
- author
- panciyan@eswincomputing.com
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • risc-v
- • codegen
- • bugfix
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-06-13T00:00:00.000Z
The RISC-V pack instruction, defined in gcc/config/riscv/crypto.md, previously used an incorrect data type iterator for its RS register. This commit changes the iterator from HISI to HX. This ensures that the register packing logic correctly matches half a target word, which is essential for accurate code generation involving RISC-V cryptographic extensions.