Landing: 3be38d59b2dd
Project / Subsystem
gcc / or1k
Date
2026-06-14
Author
Stafford Horne
Commit
3be38d59b2dda9d868ce5d9e1ec1218ce9a97129
Source
github
Perf win
No
Breaking
No
All attributes
- project
- gcc
- subsystem
- or1k
- patch_id
- —
- commit_hash
- 3be38d59b2dda9d868ce5d9e1ec1218ce9a97129
- source_type
- github
- headline
- OpenRISC fixes conditional branch instruction placement
- tldr
- GCC for OpenRISC now correctly places `cbranchsi4` instructions by explicitly declaring its clobbering of the status register flag, preventing miscompilations…
- author
- Stafford Horne
- outcome
- committed
- performance_win
- false
- breaking_change
- false
- series_id
- —
- series_parts
- []
- tags
-
- • or1k
- • bugfix
- • optimization
- • code_generation
- discussion_id_link
- —
- bugzilla_pr
- —
- date
- 2026-06-14T00:00:00.000Z
This commit resolves an issue in the OpenRISC GCC backend where the cbranchsi4 instruction was improperly placed during optimization, leading to incorrect code generation. The cbranchsi4 instruction pattern now explicitly indicates that it clobbers the status register flag (sr_f), allowing the compiler’s middle-end to avoid injecting other instructions between the comparison and the jump. This fix prevents test failures related to arithmetic overflow checks.