Landing: f9c363417791

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Project / Subsystem

gcc / risc-v

Date

2026-06-30

Author

Pan Li

Commit

f9c363417791d12b097f8c9d29f201d0b6478ed9

Source

github

Perf win

Breaking

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All attributes

project: gcc
subsystem: risc-v
patch_id: —
commit_hash: f9c363417791d12b097f8c9d29f201d0b6478ed9
source_type: github
headline: RISC-V: Add test cases for unsigned scalar SAT_MUL form 18
tldr: Adds test cases for RISC-V's unsigned scalar SAT_MUL instruction form 18.
author: Pan Li
outcome: committed
performance_win: false
breaking_change: false
series_id: —
series_parts: []
tags: • risc-v
• compiler
• testing
• instruction
discussion_id_link: —
bugzilla_pr: —
url: https://github.com/gcc-mirror/gcc/commit/f9c363417791d12b097f8c9d29f201d0b6478ed9
date: 2026-06-30T00:00:00.000Z

This commit adds a suite of test cases to validate form 18 of the RISC-V unsigned scalar SAT_MUL (saturated multiply) instruction. These tests ensure the compiler produces correct code for this specific instruction form, covering various input and output sizes.